1. Field of the Invention
The present invention relates to a dynamic semiconductor memory device, more particularly, to a dynamic semiconductor memory device wherein the potential distribution of a common opposite electrode forming one electrode of an information storing capacitor of each memory cell is equalized so that highly sensitive sense amplifiers in the memory device will not operate erroneously due to a potential difference in the common electrode.
2. Description of the Prior Art
Generally, dynamic semiconductor memory devices may be classified into two types according to how their bit lines are fed out from the sense amplifier, i.e., a folded bit-line type and an open bit-line type.
In the folded bit-line type dynamic semiconductor memory device, a pair of bit lines BL and BL led out from a sense amplifier are arranged to run in parallel from one side of the sense amplifier circuit. The opposite electrodes of the memory cell capacitors are formed from a single conductive plate.
In the open bit-line type dynamic semiconductor memory device, a pair of bit lines BL and BL led out from a sense amplifier, are arranged to run in opposite directions from the sides of the sense amplifier. The opposite electrodes of the memory cell capacitors are formed from two common conductive plates arranged at both sides of the sense amplifier. Since the two opposite electrodes straddle the area in which the sense amplifiers are formed, however, the sense amplifiers are apt to be influenced by noise due to an imbalance between the potentials of the two opposite electrodes. The sense amplifiers are so high in sensitivity that they can detect minute potential differences between the pair of bit lines determined by the information data stored in the memory cell.
To eliminate the above-mentioned problem, there has previously been proposed an open bit-line type dynamic semiconductor memory device wherein a plurality of points of the separated opposite electrodes are connected to voltage supply lines V.sub.CC or V.sub.SS running in peripheral circuits through metallic wiring lines.
Now, in a dynamic semiconductor memory device, the memory cell capacitor may be formed in two ways. In one, the common opposite electrode is connected to a higher voltage supply V.sub.CC, usually +5 V, so as to form an inversion layer in a vertical type semiconductor layer under the common opposite electrode. Accordingly, a memory cell capacitor is formed by the common electrode, the inversion layer, and an insulator layer formed on the surface of the semiconductor substrate between the common electrode and the inversion layer. In a dynamic semiconductor memory device formed in this way, the plurality of points of the common opposite electrodes are connected to the higher voltage supply V.sub.CC so to equalize the potential distribution on the common opposite electrodes.
In the other way, a depletion type metal oxide semiconductor (MOS) capacitor is formed by implanting impurities on the surface of the semiconductor substrate, so that it is not necessary to apply a positive potential to the opposite electrode for the inversion layer formation. The common opposite electrode is connected to a lower voltage supply V.sub.SS, usually 0 V. In a dynamic semiconductor memory device formed in this way, the plurality of points of the common opposite electrodes are connected to the lower voltage supply V.sub.SS so as to equalize the potential distribution on the common opposite electrodes.
However, in the above-mentioned dynamic semiconductor memory device, since circuits for generating various clock signals are provided in the peripheral circuits PC, the potentials of the voltage supply lines vary locally when these clock generator circuits operate. Since the common opposite electrodes have wide areas and are formed by relatively low conductive material such as polycrystalline silicon, the above-mentioned potential variance of the voltage supply lines is not immediately transmitted all over the common opposite electrodes. Thus, a potential difference may be produced between the opposite electrode of a selected memory cell capacitor and the opposite electrode of a corresponding dummy cell. This may cause the sense amplifiers to operate erroneously.